Multiplication circuit for multiplying analog signals by digital signals

ABSTRACT

A multiplication circuit for controlling an analog input voltage by the use of a switching signal created by a digital voltage so as to either generate an analog output or to cut-off the output. A digital input signal having a plural number of bits with given weights are introduced by use of capacitive coupling, and the resulting total becomes the multiplication result.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multiplication circuit for multiplying an analog signal by digital signals.

2. Description of the Art

In recent years, there has been controversy over the limitations of digital computers due to the exponential increase in the amount of money invested in equipment relating to minute processing technology. Thus, analog computers are now receiving greater attention. On the other hand, conventional digital storage technology should be used and thus, both digital processing and analog processing which work together are necessary. However, conventionally, a circuit which directly operates on analog and digital data without using A/D and D/A converters has not been previously known.

SUMMARY OF THE INVENTION

The present invention is invented so as to solve the problems mentioned above. The multiplication circuit, according to the present invention, is capable of directly multiplying an anolog signal and digital signals without the need for A/D or D/A converting.

A multiplication circuit according to the present invention controls an analog input voltage by the use of a switching signal created by a digital voltage so as to either generate an analog output or to cut-off the output. A digital input signal of a plural number of bits with given weights are introduced by means of capacitive coupling, and the total becomes the multiplication result. Furthermore, the invention operates by classifying the bits of digital data, then weighing them in the group and in a group unit, and then expansion of the range of values of the capacitance is controlled.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit showing an embodiment according to the present invention.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EXEMPLARY EMBODIMENTS

Hereinafter, an embodiment of a multiplication circuit according to the present invention is described with reference to the attached drawings.

In FIG. 1, a pultiplication circuit has switching means SW₀ to SW₇, wherein an anolog data V_(in) is input. The switching means are controlled for switching by each bit b₀ to b₇ of the digital signal. The switching means are classified into 2 groups: the first group being G₁ and the second group being G₂. The first group G₁ has switching means SW₀ to SW₃, and the second group G₂ has switching means SW₄ to SW₇. Each group is connected by capacitive couplings CP₁ and CP₂, respectively.

Capacitive coupling CP₁ consists of capacitances C₀ to C₃. Capacitive coupling CP₂ consists of capacitances C₄ to C₇. Capacitances C₀ to C₃ have capacities in proportion to weights b₀ to b₃, respectively. Capacitances C₄ to C₇ have capacities in proportion to weights b₄ to b₇, respectively. Furthermore, CP₁ and CP₂ are connected to a ground potential through capacitances C₁₁ and C₁₃.

The outputs of CP₁ and CP₂ are input to inverters INV₁ and INV₂, respectively, and the outputs of inverter INV₁ and INV₂ are connected through capacitive coupling CP₃. The output of CP₃ is output as analog data V_(out) through an inverter INV₃, and CP₃ is connected to a ground potential through capacitance C₃₂.

The three inverters INV₁ to INV₃ are serially connected, and accurate outputs of each inverter is maintained. In each inverter, its output is fed back to the input through C₁₀, C₁₂ and C₃₁. The capacitiies are set as follows.

    C.sub.10 -C.sub.11 =C.sub.0 +C.sub.1 +C.sub.2 +C.sub.3     (1)

    C.sub.12 -C.sub.13 =C.sub.4 +C.sub.5 +C.sub.6 +C.sub.7     (2)

    C.sub.31 -C.sub.32 =C.sub.21 +C.sub.22                     (3)

If the gain of INV₁ to INV₃ is defined as G, the voltages impressed on C₀ to C₇ are defined as V₀ to V₇, the input voltages of INV₁ and INV₂ are defined as V₁₁, and V₁₂, respectively, the output voltages are defined as V₂₁ and V₂₂, respectively, and the input voltage of INV₃ is defined as V₃₁, then formulas (4), (5) can be obtained. ##EQU1##

Under certain conditions formulas (6) and (7) can be established.

    C.sub.21 V.sub.21 +C.sub.22 V.sub.22 +C.sub.31 (V.sub.31 -V.sub.out)+C.sub.32 V.sub.31 =0                          (6)

    V.sub.21 =GV.sub.11 ; V.sub.22 =GV.sub.12 ; and V.sub.out =GV.sub.31(7)

Then formulas (8) and (9) can be defined as follows. ##EQU2##

Formula (10) is then obtained.

    V.sub.out =(C.sub.21 V.sub.21 +C.sub.22 V.sub.22)          (10)

When SW₁ is connected with V_(in) or the ground potential corresponding to b₀ to b₇, and V_(i) is equal to V_(in) or 0, and following formulas are obtained.

    C.sub.1 =2.sup.i ×Cu (i=0 to 3)                      (11)

    C.sub.i =2.sup.i-4 ×Cu (i=4 to 7)                    (12)

    C.sub.11 =C.sub.13 =C.sub.32 =Cu                           (13)

wherein Cu is an unit capacity

    C.sub.22 =2.sup.4 ×C.sub.21                          (14)

    C.sub.31 =2.sup.4 ×Cu                                (15)

Therefore, the final output becomes a multiplication result of an anolog signal and digital signals.

Formula (16) can then be defined as follows. ##EQU3##

When formula (17) is true, then formula (18) is obtained.

    C.sub.31 =2.sup.3 ×Cu                                (17) ##EQU4##

A level of formula (18) is twice that of formula (16). By this type of level controlling, a moving are can be selected.

As shown by formula 12, bits b₀ to b₃ and b₄ to b₇ of digital data are in different groups and a weight is given to each of the bits. The order of 2³ is sufficiently in the range of capacticances C₀ to C₇, because the multiplication result of higher groups are given a weight corresponding to the group.

As mentioned above, a multiplication circuit according to the present invention controls an analog voltage by the use of a switching signal of a digital voltage so as to either generate an anolog output or to cut off the output. A digital input signal of a plural number of bits are given weights by means of capacitive coupling, and the total becomes a multiplication result. Furthermore, the invention operates by classifying the bits of digital data, then weighing them in the group and in a group unit, and then expansion of the range of values of the capacitance is controlled. 

What is claimed is:
 1. A multiplication circuit for multiplying an analog signal and a digital signal having bits comprising:a plurality of first capacitances arranged so as to correspond to groups in which said bits of said digital signal are classified, each said first capacitance having a capacitance value corresponding to a bit weight to be assigned to said bits of each said corresponding group; a plurality of second capacitances arranged so as to correspond to each bit that is included in each of said corresponding groups, each said second capacitance having a capacitance values corresponding to a bit weight to be assigned to each said bit; and a plurality of switching means for connecting said analog signal to each said first capacitance.
 2. A multiplication circuit according to claim 1, wherein said digital data includes 8 bits.
 3. A multiplication circuit according to claim 1, wherein each said group includes 4 bits.
 4. A multiplication circuit according to claim 1, further comprising an amplifier having a feed back system, and wherein an output of said multiplication circuit is voltage compensated by said amplifier. 